A digital circuit can be represented as a set of interconnected logic gates. Static Timing Analysis (STA) is a method of computing the expected timing of a digital circuit without requiring expensive simulation. To perform static timing analysis, the arrival time at all the primary inputs are first annotated. Then the arrival time is propagated forward by adding delays along the interconnects and gates.
This process continues until all primary outputs are reached.
In current approaches, data generated during the arrival time propagation is all stored in the computer's random-access memory (RAM). The application's memory footprint is proportional to the size of the design. For modern system-on-a-chip (SoC) designs, traditional static timing analysis requires on the order of 30 GB (gigabytes) or more of memory. Owing to the memory needed, the hardware requirement can be prohibitively expensive. What is needed is a method and system for static timing analysis that operates using substantially less than 30 GB, even when the design is a SoC design.
Moreover, current approaches to static timing analysis process or execute only one thread at a time (FIG. 1A). Single threaded execution—executing a single thread at a time—makes, as current trend favors larger designs, for a correspondingly lengthy analysis time. Those of average skill in the relevant art are familiar with “gate” as a unit of design, and “thread” as a unit of execution.
Commencing with design input 11, all gates are levelized into a single sequential order 13. Beginning at a first gate 15, the gate is processed 17 and the analysis then proceeds to the next gate 19, until the last gate is reached 20 and the design analysis is done 21. It can be appreciated, then, that data flow requires significant RAM, as all the data for the entire design ins in RAM, all associated calculations—the results of the analysis—must all be accommodated in RAM.
What is needed is a method of performing static timing analysis such that the amount of required RAM does not increase as the size of the design under analysis increases. Further, what is needed is a faster approach to design analysis, including static timing analysis.